For researchers outside NUS, please request access through Xilinx University Program.
For researchers at NUS, please apply through the following link: NUS HACC Account Registration.
The user account expires after one year or there is no login event within two months. You will get a notification from NUS of this event one month in advance. If you plan to keep using the resources, please follow the instruction in the notification mail.
We have the following FPGA boards.
| GPU/FPGA Cluster | Hardware Setup | Shell/Arch Version | XRT Version | Toolchain Version |
|---|---|---|---|---|
| GPU/FPGA Cluster | VCK5000 x2 | xilinx_vck5000_gen4x8_qdma_2_202220_1 | 2.14.384 | Vitis 2022.2 |
| U55C x6 | xilinx_u55c_gen3x16_xdma_3_202210_1 | 2.14.384 | Vitis 2022.2 | |
| MI210 x12 | gfx90a | - | ROCm-5.1.0 | |
| U250 Cluster | Alveo U250 x4 | xilinx_u250_gen3x16_xdma_3_1_202020_1 | 2.14.354 | Vitis 2021.2 |
| U280 Cluster | Alveo U280 x4 | xilinx_u280_xdma_201920_3 | 2.14.354 | Vitis 2021.2 |
| VCK5000 Cluster | VCK5000 x4 | xilinx_vck5000_gen4x8_qdma_2_202220_1 | 2.14.384 | Vitis 2022.2 |
| U50 Single Node | Alveo U50 x1 | xilinx_u50_gen3x16_xdma_201920_3 | 2.14.354 | Vitis 2021.2 |
| GPU Cluster | MI25 x8 | gfx906 | - | ROCm-5.1.0 |
Access through SSH:
ssh username@xacchead.d2.comp.nus.edu.sgPlease following the instructions in the email that contains your account's information to set up the 2FA authentication.
XACC clusters now only support the Vitis Design Flow. Benefiting from XRT environments and C/C++ based HLS tools, FPGA developlors can easy test their code in real hardware, and algorithm designers can ignore the hardware details. If you want to evaluate some RTL modules, we suggest you try the mix programming with Vitis following this and examples.
Users should then use the following command to setup the environment:
# Set XRT Environment
source /opt/xilinx/xrt/setup.sh
# Set Vitis Environment, for the node installed Vitis 2021.2
source /opt/Xilinx/Vitis/2021.2/settings64.sh
Please following this on how to write a Slurm job to utilize FPGAs.
/data is a shared path in all compute nodes for users to store insensitive data.
Please keep your data size within 50GB.
We have installed VNC server in our cluster for a better experience on waveform-based FPGA simulation. To enable it, please follow this to setup the VNC service for your account.
If you need help (e.g., software installation), you can submit issues in here.
You also can join our Telegram Group (HACC@NUS Forum) for emergency help (e.g., registration problems).
In case you forgot your account's password, you can email xacc.nus.user@gmail.com with the following information
Subject: Reset password Context: Account: your_username
We would like to thank Xilinx for the hardware donation.
AMD encourages HACC users to acknowledge AMD’s support of your research in your presentations, papers, posters, and press releases. A brief statement such as the one below is recommended.
This work was supported in part by AMD under the Heterogeneous Accelerated Compute Clusters (HACC) program (formerly known as the XACC program - Xilinx Adaptive Compute Cluster program).
