From b108f7564235467538aa220c1c7b3a312cce05d6 Mon Sep 17 00:00:00 2001 From: Sam Winchenbach Date: Mon, 19 Oct 2026 16:47:53 -0400 Subject: [PATCH] arch: sc5xx: skip CDU0 CLKINSEL write on SC846 cdu_init() unconditionally writes CONFIG_CDU0_CGU1_CLKIN to REG_CDU0_CLKINSEL (0x3108F044) to select the CGU1 input clock. The CLKINSEL register is optional in the CDU block and is not implemented on ADSP-SC846. Skip the write on SC846 so the SPL does not access an unimplemented register during early clock initialisation. Fixes: 3285a564d2b ("arch: sc5xx: Add SC846 DDR init hooks") Signed-off-by: Sam Winchenbach --- arch/arm/mach-sc5xx/Kconfig | 9 ++++++++- arch/arm/mach-sc5xx/init/clkinit.c | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index 3f6468ba743e..4da914e5990f 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -59,9 +59,16 @@ config SC846 select GICV3_SUPPORT_GIC600 select GIC_600_CLEAR_RDPD select MMC_SDHCI_ADMA_FORCE_32BIT + select FIXED_CGU1_INPUT_CLOCK select NOP_PHY if PHY endchoice +config FIXED_CGU1_INPUT_CLOCK + bool + help + The CDU has no CLKINSEL register, so the CGU1 input clock is + fixed to SYS_CLKIN0 and cannot be selected. + if SC57X config TARGET_SC573_EZLITE @@ -572,7 +579,7 @@ config CGU1_DIV_S1SELEX SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX config CDU0_CGU1_CLKIN - int "CDU0 CGU1 CLKINn Select" + int "CDU0 CGU1 CLKINn Select" if !FIXED_CGU1_INPUT_CLOCK default 0 range 0 1 help diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c index dcf328190647..77c7065df4e7 100644 --- a/arch/arm/mach-sc5xx/init/clkinit.c +++ b/arch/arm/mach-sc5xx/init/clkinit.c @@ -524,7 +524,13 @@ void cdu_init(void) { while (readl(REG_CDU0_STAT) & 0xffff) ; - writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL); + + /* + * Some parts (e.g. SC846) have no CLKINSEL register; CGU1 is + * fixed to SYS_CLKIN0 there. + */ + if (!IS_ENABLED(CONFIG_FIXED_CGU1_INPUT_CLOCK)) + writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL); CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0); CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1);