A question about RISC-V pipeline stages

[Syuennykok]

I noticed that OpenASIP supports three and four pipeline stages for RISC-V generator.
How could I change the generator configuration? Is it possible to customize pipeline stages?

[karihepola]

Sorry for the late reply. You can change it by setting the amount of delay slots to three in the ADF. Do this by opening the included rv32im.adf with ProDe:

prode rv32im.adf

Select the control unit (GCU) and set the delay slot parameter there. The generated RTL should have enabled an extra register to the instruction fetch unit accordingly once invoking generateprocessor.