Register interface bus to a section defined as external

[martin-tanguay]

Hi,

When I define a register section as external (such as registers in a RAM), the interface bus uses peakRDL internal CPUIF protocol. If my module uses the AXI4-Lite protocol, is it possible to have the external bus use the same protocol ?

Thanks !

Martin

[martin-tanguay]

@amykyta3 Any idea ?

[amykyta3]

The intent of the external mechanism for PeakRDL-regblock is to provide a fall-back mechanism to adapt to "special" registers that do not fit the usual specifications of SystemRDL. Adapting the interface back to a standard protocol like AXI is certainly possible, but a little out of scope for the PeakRDL-regblock project. I know some folks have been using externals as a mechanisms to make a rudimentary "bus decoder" out of a reg block but this ends up resulting in some performance/scaling issues as it was not really optimized to be used that way.

Another project that may interest you is @arnavsacheti 's PeakRDL-BusDecoder which intends to generate a simple 1-to-N interconnect. In the future I hope to get more involved with that project and expand it to more protocols. Something like this might be a better fit for your application.

[martin-tanguay]

OK thanks for the answer !