Repository navigation
feat(minimax-h3): add a single-GPU AMD ROCm recipe (aiter attention, 4-step Turbo LoRA), measured on MI355X - #1534
Open
stayinalive181 wants to merge 1 commit into
Conversation
Author
|
@helloyongyang gentle ping on this one. I re-ran it on current main (0c2edc1) on one MI355X, with the same image and method as the table above:
While I was at it, I checked whether the video VAE should also go through aiter, as SGLang does for H3 in sgl-project/sglang#39450. There the VAE's SDPA was pinned to the math kernel on gfx950. On this image it is not:
So I left it out of this PR. Happy to send it separately if you want it. |
…on and the 4-step Turbo LoRA configs/platforms/amd_rocm/minimax_h3_t2av_4step.json is the dmd/minimax_h3_bf16_4step.json preset with attn_type aiter_attn and every component resident (no CPU offload, no AdaLN cache): one 288 GB MI355X holds the BF16 DiT, the text encoder and both VAEs. The LoRA is merged at load (lora_dynamic_apply false), 3% faster per step than dynamic apply. scripts/platforms/amd_rocm/run_minimax_h3_t2av_4step.sh launches it in the same shape as the other scripts for this platform.
stayinalive181
force-pushed
the
amd-rocm-minimax-h3-recipe
branch
from
October 21, 2026 09:04
a5f5cf4 to
07978da
Compare
Author
|
Rebased onto current main (b7bc39f). The PR merges cleanly again. Changes in this update:
The PR is now the two new files under |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What
A single-GPU AMD ROCm recipe for MiniMax-H3 T2AV with the 4-step 768p Turbo LoRA:
configs/platforms/amd_rocm/minimax_h3_t2av_4step.json: thedmd/minimax_h3_bf16_4step.jsonpreset (as simplified in refactor: simplify inference configs and example scripts(v3) #1592) withattn_type: aiter_attn(the attention backendlightx2v_platformregisters for ROCm) and every component resident (cpu_offload,use_adaln_cache, text-encoder and VAE offload off). A 288 GB MI355X holds the BF16 DiT, the text encoder and both VAEs at once, so the AdaLN cache and block offload that the shared preset needs on smaller cards are not needed here.lora_dynamic_applyisfalse: merging the LoRA at load was 3% faster per step than applying it dynamically on this card.scripts/platforms/amd_rocm/run_minimax_h3_t2av_4step.sh: launcher in the same shape as the existingrun_wan21_t2v.shfor this platform.configs/platforms/amd_rocm/had only the Wan 2.1 and Qwen-Image presets, and nothing in the repo showed H3 running on ROCm.Measured
One AMD Instinct MI355X (gfx950, 288 GB). Base image
lmsysorg/sglang:v0.5.20-rocm724-mi35x(torch 2.11.0+rocm7.2, HIP 7.2, aiter from the image), LightX2Vmainat5216198548installed withpip install -e . --no-depsplusrequirements.txtwithout the torch lines. Diffusers component layout fromMiniMaxAI/MiniMax-H3(roottransformer/,text_encoder/,tokenizer/,processor/,vae/,audio_vae/), Turbo LoRAminimax_h3_fl2v_turbo_4step_v1.0_768p_bf16.safetensors, seed 42,--task t2av. Second run of each shape after a warm run; times are the[Profile]lines.RUN pipelinelora_dynamic_apply: false)true)--size 544 960 --num_frames 124Model load is 95–110 s from the page cache. The 1344×768 output is 15.08 s at 24 fps with a stereo track and looks right. The first step of every run carries aiter's
fmha_v3kernel load, hence the slightly slower firstinfer_main.Notes for anyone repeating this
transformer/at the originalFL2VA/transformercheckpoint fails at load withKeyError: 'proj_in.weight', as the guide already warns.scripts/base/base.shexportsPYTORCH_ALLOC_CONF=expandable_segments:True. That was fine on this ROCm 7.2 stack; on therocm/pytorch7.14.1 image the same setting made allocations fail early for us in another project, so if a run dies with an out-of-memory error far below the card's capacity, unset it first.Happy to add an MI300X row if someone can run the script there.