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feat(minimax-h3): add a single-GPU AMD ROCm recipe (aiter attention, 4-step Turbo LoRA), measured on MI355X - #1534

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@stayinalive181

@stayinalive181 stayinalive181 commented Sep 19, 2026 •

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What

A single-GPU AMD ROCm recipe for MiniMax-H3 T2AV with the 4-step 768p Turbo LoRA:

  • configs/platforms/amd_rocm/minimax_h3_t2av_4step.json: the dmd/minimax_h3_bf16_4step.json preset (as simplified in refactor: simplify inference configs and example scripts(v3) #1592) with attn_type: aiter_attn (the attention backend lightx2v_platform registers for ROCm) and every component resident (cpu_offload, use_adaln_cache, text-encoder and VAE offload off). A 288 GB MI355X holds the BF16 DiT, the text encoder and both VAEs at once, so the AdaLN cache and block offload that the shared preset needs on smaller cards are not needed here. lora_dynamic_apply is false: merging the LoRA at load was 3% faster per step than applying it dynamically on this card.
  • scripts/platforms/amd_rocm/run_minimax_h3_t2av_4step.sh: launcher in the same shape as the existing run_wan21_t2v.sh for this platform.

configs/platforms/amd_rocm/ had only the Wan 2.1 and Qwen-Image presets, and nothing in the repo showed H3 running on ROCm.

Measured

One AMD Instinct MI355X (gfx950, 288 GB). Base image lmsysorg/sglang:v0.5.20-rocm724-mi35x (torch 2.11.0+rocm7.2, HIP 7.2, aiter from the image), LightX2V main at 5216198548 installed with pip install -e . --no-deps plus requirements.txt without the torch lines. Diffusers component layout from MiniMaxAI/MiniMax-H3 (root transformer/, text_encoder/, tokenizer/, processor/, vae/, audio_vae/), Turbo LoRA minimax_h3_fl2v_turbo_4step_v1.0_768p_bf16.safetensors, seed 42, --task t2av. Second run of each shape after a warm run; times are the [Profile] lines.

output LoRA DiT, 4 steps video VAE decode audio VAE decode text encoder RUN pipeline clip s / pipeline s
1344×768, 362 frames (15.08 s) merged (lora_dynamic_apply: false) 21.4 + 20.6 + 20.6 + 20.7 = 83.3 s 17.4 s 2.3 s 2.3 s 111.5 s 0.135
1344×768, 362 frames (15.08 s) dynamic (true) 22.1 + 21.4 + 21.4 + 21.5 = 86.4 s 17.5 s 2.3 s 2.4 s 114.6 s 0.132
960×544, 124 frames (5.17 s), --size 544 960 --num_frames 124 dynamic 2.4 + 1.6 + 1.6 + 1.6 = 7.0 s 5.0 s 2.3 s 2.4 s 18.2 s 0.284

Model load is 95–110 s from the page cache. The 1344×768 output is 15.08 s at 24 fps with a stereo track and looks right. The first step of every run carries aiter's fmha_v3 kernel load, hence the slightly slower first infer_main.

Notes for anyone repeating this

  • The model directory must be the Diffusers component layout at the repo root; pointing transformer/ at the original FL2VA/transformer checkpoint fails at load with KeyError: 'proj_in.weight', as the guide already warns.
  • scripts/base/base.sh exports PYTORCH_ALLOC_CONF=expandable_segments:True. That was fine on this ROCm 7.2 stack; on the rocm/pytorch 7.14.1 image the same setting made allocations fail early for us in another project, so if a run dies with an out-of-memory error far below the card's capacity, unset it first.

Happy to add an MI300X row if someone can run the script there.

@stayinalive181

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@helloyongyang gentle ping on this one. I re-ran it on current main (0c2edc1) on one MI355X, with the same image and method as the table above:

  • RUN pipeline is 111.6 s at 1344×768 / 362 frames and 18.2 s at 960×544 / 124 frames, the same as the table.
  • The PR still merges cleanly.
  • The 4-step preset it builds on (minimax_h3/dmd/minimax_h3_bf16_4step.json) has not changed since.

While I was at it, I checked whether the video VAE should also go through aiter, as SGLang does for H3 in sgl-project/sglang#39450. There the VAE's SDPA was pinned to the math kernel on gfx950. On this image it is not:

  • Torch SDPA already takes the flash kernel for the VAE's attention, at 0.10 ms per call against 0.97 ms for math.
  • Attention is about 7% of the decode. The largest share is the linear layers' GEMMs.
  • Routing it through aiter needs a small dense-input path in aiter_attn and aiter_attn in the VAE's allowed list. It took video VAE decode from 17.5 s to 16.6 s at 1344×768 and from 5.2 s to 5.1 s at 960×544, about 1% of the pipeline.

So I left it out of this PR. Happy to send it separately if you want it.

…on and the 4-step Turbo LoRA

configs/platforms/amd_rocm/minimax_h3_t2av_4step.json is the
dmd/minimax_h3_bf16_4step.json preset with attn_type aiter_attn and every
component resident (no CPU offload, no AdaLN cache): one 288 GB MI355X
holds the BF16 DiT, the text encoder and both VAEs. The LoRA is merged at
load (lora_dynamic_apply false), 3% faster per step than dynamic apply.
scripts/platforms/amd_rocm/run_minimax_h3_t2av_4step.sh launches it in
the same shape as the other scripts for this platform.
@stayinalive181
stayinalive181 force-pushed the amd-rocm-minimax-h3-recipe branch from a5f5cf4 to 07978da Compare October 21, 2026 09:04
@stayinalive181

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Rebased onto current main (b7bc39f). The PR merges cleanly again. Changes in this update:

  • README. The edit to scripts/minimax_h3/README.md is dropped. The reworked guide lists only representative configs under configs/minimax_h3/, so a row for a platform recipe no longer fits there.
  • Config. lazy_load, unload_modules and audio_sampling_rate are removed from the config, matching how refactor: simplify inference configs and example scripts(v3) #1592 simplified the dmd/minimax_h3_bf16_4step.json preset it builds on. All three are defaults.

The PR is now the two new files under configs/platforms/amd_rocm/ and scripts/platforms/amd_rocm/. The numbers in the description and the 10-06 re-run on 0c2edc1 still apply; this update only drops keys that are defaults.

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