Inference: properly size barrier slots for symmetric memory allocations

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What does this PR do?

The default size of the signal pad ptrs array is 32 * 72 * 4 (https://github.com/yang-yu-hang/pytorch/blob/main/torch/csrc/distributed/c10d/symm_mem/CUDASymmetricMemoryTypes.hpp#L25-L27). The 32 is assumed to be default number of blocks, 72 accounts for all GPUs in NVL72 domain, and 4 is 4 bytes per value, since each barrier slot is an int32.

However for larger number of blocks, ranks will be writing out of the memory region allocated for the signal pad ptrs, so we should explicitly set the size of the barrier slots as a function of world size and the number of blocks.

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