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PeakRDL-regblock

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Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl-regblock.readthedocs.io

asic csr fpga registers systemrdl systemrdl-compiler systemverilog systemverilog-hdl

LGPL-3.0 license

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Name		Name	Last commit message	Last commit date
.github		.github
docs		docs
hdl-src		hdl-src
src/peakrdl_regblock		src/peakrdl_regblock
tests		tests
.gitignore		.gitignore
.readthedocs.yaml		.readthedocs.yaml
CONTRIBUTING.md		CONTRIBUTING.md
LICENSE		LICENSE
MANIFEST.in		MANIFEST.in
README.md		README.md
pyproject.toml		pyproject.toml

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PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

About

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl-regblock.readthedocs.io

asic csr fpga registers systemrdl systemrdl-compiler systemverilog systemverilog-hdl

LGPL-3.0 license

Custom properties

88 stars

20 watching

Report repository

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