Issues

• Bug: the rp2350 part carries RP2040 pin numbers, so a board ordering RP2350A is laid out to another device

  absmach/synth#152 · Filter by author JeffMboya opened on Oct 13, 2026

• Declare silkscreen reference-label placement in the part and sidecar schemas

  absmach/synth#150 · Filter by author nyagamunene opened on Oct 13, 2026

• Bug: match_length and max_skew are dropped at the export boundary, and no .kicad_dru is written

  absmach/synth#147 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: esp32_c3_mini names a symbol and footprint that do not exist, and invents two USB pins

  absmach/synth#146 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: routed ground copper shorts the HDMI receptacle's signal pads, and the board reports only open nets

  absmach/synth#143 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: a declared keepout never reaches the exported board, so it constrains nothing

  absmach/synth#142 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: no via or fanout rule can be declared, so a BGA escape cannot be specified

  absmach/synth#137 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: via-in-pad cannot be declared by a board or a profile, only by a CLI flag

  absmach/synth#136 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: the capability descriptor denies skew enforcement that E-SYNTH-DRC-014 performs

  absmach/synth#135 · Filter by author JeffMboya opened on Oct 13, 2026

• Bug: edge legalisation nudges a pinned connector by the same offset every run, so placement never converges

  absmach/synth#133 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: a through via's layer span is read as two layers, so it never reaches an inner-layer plane

  absmach/synth#130 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: the language reference omits class on connect, so every netclass an agent writes is inert

  absmach/synth#129 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: every plane net is poured on every inner layer, so two rails starve each other

  absmach/synth#128 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: a net with a gap between collinear tracks is reported connected

  absmach/synth#123 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: a controlled-impedance pair cannot be pinned to a layer

  absmach/synth#118 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: only ground can be poured, so a multi-rail board cannot route

  absmach/synth#117 · Filter by author JeffMboya opened on Oct 12, 2026

• Bug: the routed matrix leaves two boards failing the gate

  absmach/synth#98 · Filter by author JeffMboya opened on Oct 9, 2026

• Bug: no BGA part, and lengths cannot be matched between nets

  absmach/synth#97 · Filter by author JeffMboya opened on Oct 9, 2026

• Bug: several parts name KiCad symbols and footprints that do not exist

  absmach/synth#96 · Filter by author JeffMboya opened on Oct 9, 2026

• Bug: every board fails the gate because no router is installed in CI

  absmach/synth#95 · Filter by author JeffMboya opened on Oct 9, 2026
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• Several shipped parts have pin maps that do not match their footprints

  absmach/synth#87 · Filter by author JeffMboya opened on Oct 7, 2026
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• ESD parts' surge rating is counted as steady current, so protected boards fail the power budget

  absmach/synth#83 · Filter by author JeffMboya opened on Oct 6, 2026

• A USB-C sink with floating CC pins gets no diagnostic

  absmach/synth#82 · Filter by author JeffMboya opened on Oct 6, 2026

• Add a precision analog front-end board to the Class B qualification matrix

  absmach/synth#69 · Filter by author nyagamunene opened on Oct 5, 2026

• Compare the Class B matrix with a human reference and record reviewer sign-off

  absmach/synth#68 · Filter by author nyagamunene opened on Oct 5, 2026