Add adaq2387x support - #3496
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| #include "zynq-zed-adv7511-adaq23875.dtsi" | ||
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| &adaq23875 { | ||
| adi,use-one-lane; |
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Replace the deprecated adi,use-two-lanes property with the updated
convention where two-lane operation is the default. Introduce
adi,use-one-lane to explicitly select single-lane mode.
the devicetree is not really about defaults, but the topology.
Not clear how adi,use-two-lanes -> adi,use-one-lane is future-proof.
Where/when was that discussed?
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I'd meant to ask about it in the pull request as i wasn't sure of what convention to follow when naming this property.
currently, we have:
- num-lanes(int)
- lane-mode(enum)
- one-lane(my commits change it to two)
Having two lanes as the default for the adaq drivers helps achieve the maximum sample rate of the chip, which is why i thought it made sense. It's worth discussing the exact naming convention for this property in order to fall in line with other adc implementations
LLM reviewThis series adds ADAQ23875/76/78 (LTC2387-based) support: a driver cleanup run: 32902194316
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Add the adi,channels DMA configuration, setting a 32-bit source bus width (aligned with the 18-bit ADC output) and a 64-bit destination width. Replace the deprecated adi,use-two-lanes property with the updated convention where two-lane operation is the default. Introduce adi,use-one-lane to explicitly select single-lane mode. Also fix the device title and add an HDL configuration note. Signed-off-by: Stanca Pop <stanca.pop@analog.com> Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
… default Fix the duty offset boundary check to also handle the equal case, and compute sampling_freq from the actual PWM period length rather than the requested frequency. Change the lane mode default to two-lanes, matching the reference HDL which ships with TWOLANES=1, and introduce adi,use-one-lane for boards wired for single-lane output. Signed-off-by: Stanca Pop <stanca.pop@analog.com> Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
Add device tree support for the ADAQ23875 (LTC2387-16, 16-bit) and ADAQ23878 (LTC2387-18, 18-bit) uModule ADCs on the Xilinx Zedboard. Shared carrier pieces live in adaq2387x.dtsi: the 4.096 V reference regulator, the 120 MHz reference clock the HDL produces, the DMA controller, the PWM generator driving CNV and CLK_EN, and the GPIOs for the test-pattern and power-down pins. Per-part dtsis add the matching DMA data width and instantiate the ADC node, and each part gets a two-lane leaf .dts plus a -1lane variant for the reduced-throughput bitstream. Both parts declare adi,gain-milli for their front-end amplifier gain: the ADAQ23875 is fixed at 2, while the ADAQ23878 is pin-strapped and defaults here to 0.87. Override the FMC FRU ID EEPROM to atmel,24c32 for these boards. The EV-ADAQ2387xFMCZ carries a 24AA32A, which is 4 kbyte and needs 16-bit addressing, whereas zynq-zed-adv7511.dtsi declares the 256-byte 8-bit part. That node sits on axi_iic_fmc, reached through FMC LPC pins C30 and C31, so it describes the daughtercard rather than the carrier and is overridden per board instead of in the shared file. Signed-off-by: Stanca Pop <stanca.pop@analog.com> Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
Document adi,gain-milli, the front-end amplifier gain of the ADAQ2387x modules expressed as gain * 1000. The ADAQ23875 is fixed at 2; the ADAQ23876 and ADAQ23878 are pin-selectable over 0.37 to 2.25. The bare ltc2387-* parts have no amplifier, so they default to unity. Document adi,use-one-lane, which selects one-lane DDR output instead of the two-lane default, and vref-supply, which the driver already consumes. Add the additionalProperties constraint and correct $id to match the file name, both required by the current dt-schema meta-schema. Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
Consolidated cleanup pass on the LTC2387 driver in preparation for the
ADAQ2387x variants:
- Fix typos in the vref regulator error string and in the PWM
disable callback name.
- Change sampling_freq to u32 and drop unused struct fields.
- Factor the DDR test patterns into named macros.
- Split the ADAQ2387x compatibles into distinct info entries with
per-variant .name so indio_dev->name reflects the actual board.
- Cache vref_mv at probe instead of re-reading the regulator in
read_raw.
- Clamp the conversion period to the clk_gate period so the PWM
core's stricter duty > period check is satisfied.
Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
The ADAQ2387x modules place a fully-differential amplifier ahead of the LTC2387 die, so a code read back from the converter corresponds to a smaller voltage at the SMA input than at the die. Read the amplifier gain from adi,gain-milli and fold it into IIO_CHAN_INFO_SCALE so in_voltage_scale is referred to the SMA input. The default is carried per compatible rather than as a single constant: the bare ltc2387-* parts have no amplifier and so default to unity, while the adaq2387x parts default to 2. Using one global default would have halved the reported scale on the plain LTC2387 boards, which do not set the property. Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
sampling_freq was derived from the conversion period the driver asked the PWM core for, rather than the one the hardware ends up running. The core truncates the period to whole ref_clk cycles, and a cycle count is generally not an integer number of nanoseconds: at 120 MHz a 15 MHz conversion period is 66.67 ns, so it has to be requested as 67 ns. Dividing NSEC_PER_SEC by that rounded-up period reported 14.93 MHz for a pin running at exactly 15 MHz. The error is worse in one-lane mode, where the clk_en duty cycle forces the period clamp and lands further from a cycle boundary: an 18-bit part at 120 MHz reported 11.11 MHz while converting at 12 MHz, off by 7.4%. That is enough to visibly misplace FFT bins for anyone who trusts in_voltage_sampling_frequency. Mirror the core's truncation to recover the cycle count and divide the reference clock by it, which is exact for every supported combination of reference clock, resolution and lane mode. Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
read_raw() has always handled IIO_CHAN_INFO_SCALE, but no channel advertised it, so IIO never created the attribute and the case was unreachable from userspace. Applications had to hardcode the conversion from raw codes to volts. Advertise it via info_mask_shared_by_type, which yields a single in_voltage_scale shared by every voltage channel rather than one attribute per channel: the scale depends on the reference voltage and the front-end gain, both of which are device-wide. Using info_mask_shared_by_all instead would name the attribute plain "scale", which libiio does not recognise as the channel scale. On an ADAQ23875 with a 4.096 V reference and the fixed gain of 2 this reports 0.062500000 mV/LSB, so the 16-bit code range spans the 4.096 V peak-to-peak the SMA inputs accept. Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
Introduce a common dtsi and two leaf .dts files for the ADAQ23876 on Zedboard. The 23876 shares the LTC2387-16 die with the 23875, so the digital protocol and DMA path are identical; only the front-end amplifier gain differs. Default the gain to 0.87 (adi,gain-milli = 870); the -1lane variant additionally sets adi,use-one-lane for the reduced-throughput HDL bitstream. Signed-off-by: Nicolae-Daniel Deaconescu <Nicolae-daniel.deaconescu@analog.com>
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PR Description
Add Linux support for the ADAQ23875, ADAQ23876, and ADAQ23878 ADCs on the Xilinx Zedboard. All three parts wrap the LTC2387 behind an integrated fully-differential amplifier. The 23875 has fixed FDA gain of 2; the 23876 and 23878 have a board-strapped gain (0.37, 0.73, 0.87, 1.38, or 2.25) that the driver needs to reflect in in_voltage_scale.
Changes:
Tested on ADAQ23875 + Zedboard with one and two lane bitstreams
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