{bp-19783} arch/tricore: drop iLLD dependency in cache and perf paths

[jerpelea]

Summary

Remove the Infineon iLLD dependency from the arch/tricore cache and
performance-counter paths, replacing the iLLD intrinsics and register
structures with direct CSR (Core Special Function Register) accesses.

The series contains three commits, kept separate to match the internal
development history:

add tricore_mtcr and tricore_mfcr macros — introduce
tricore_mtcr() / tricore_mfcr() inline-assembly wrappers for the
MTCR/MFCR instructions in arch/arch.h, so arch/tricore code can access
CSRs without the iLLD intrinsics.
cachecode donot depend on illd — replace the iLLD register structures
(Ifx_CPU_PCON0/1/2, Ifx_CPU_DCON0/1/2) and IfxCpu_cfg.h cache macros
in tricore_cache.c with tricore_mtcr()/tricore_mfcr() plus locally
defined PCON/DCON CSR numbers and bit masks. barriers.h UP_ISB() /
UP_DSB() now emit the isync / dsync instructions directly instead of
the iLLD __isync() / __dsync() intrinsics.
perf.c donot depend on illd — replace IfxCpu_resetAndStartCounters()
and IfxCpu_getClockCounter() with direct CCTRL/CCNT CSR accesses.

The CSR register numbers previously pulled in from the iLLD IfxCpu_reg.h
are now defined locally in each file that needs them.

Impact

RELEASE

Testing

CI

[jerpelea]

do not restart Ci until #19814 is merged