Verilog: handle deassign, release, and disable in convert_statement - #1949
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Verilog: handle deassign, release, and disable in convert_statement#1949kroening wants to merge 1 commit into
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We should have one or more tests here. |
These procedural statements require no type-checking (they operate on already-typed lvalues). The typecheck pass was throwing 'unexpected statement' for them after the elaboration pass started accepting them. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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Now with a test for each of the statements. |
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Summary
deassign,release, anddisableare valid procedural statements that reachconvert_statementbut were not handled, causing a'unexpected statement'error. They require no type-checking — add no-op cases for them.🤖 Generated with Claude Code