Verilog: fold Verilog-specific constructs when propagating constants in synthesis

[kroening]

When synthesising a blocking assignment, synth_assign tries to simplify
the right-hand side to a constant so the value can be propagated (needed,
among other things, to unroll for/while loops by evaluating their guard
each iteration). It used the plain simplifier, which does not know how to
reduce Verilog-specific constructs such as replication ({n{x}}) to a
constant.

As a result a loop whose bit-vector loop variable is initialised with a
replication, e.g.

for(data_mask = {1'b1, {DW-1{1'b0}}}; data_mask != 0;
    data_mask = data_mask >> 1)

left data_mask non-constant, so synthesis reported "synthesis failed to
evaluate loop guard". Uses the Verilog-aware simplifier instead, which
lowers replication to a concatenation before folding. The result is only
used when it is constant, so non-constant right-hand sides are unaffected.

This is the root cause of the loop-guard failures for the LogikBench
blocks/ethmac (rtl/eth_lfsr.v:235) and blocks/lfsr (rtl/lfsr.v:235)
benchmarks.

New regression test: regression/verilog/synth_loop_guard_bitvector1.