Verilog: arrays of interface ports - #2079
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tautschnig
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SystemVerilog allows an interface port to have unpacked dimensions, i.e.,
an array of interface ports (IEEE 1800-2017 section 25.4, and
ansi_port_declaration in A.1.3). The parser rejected the dimension:
interface ifc;
logic x;
modport mp (input x);
endinterface
module m(ifc.mp a[0:3]); // syntax error, unexpected '['
endmodule
Each element of the array yields an interface instance of its own, named
bus[0], bus[1], and so on, and each of those is bound to the interface
instance that the port connection gives for that element. Selecting an
element of such an array, e.g. bus[0].some_signal, resolves to the member
of the interface instance for that element. Any number of dimensions is
supported.
The array elements may be given as an assignment pattern, one interface
instance per element, or by the name of another array of interfaces, which
is how a module passes on an array of interface ports that it has itself
been given.
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This implements SystemVerilog unpacked dimensions for interface ports (IEEE 1800-2017 section 25.4, and
ansi_port_declarationin A.1.3).Minimal example