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Verilog: parse packages before the files that import them - #2082

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Verilog: parse packages before the files that import them#2082
kroening wants to merge 2 commits into
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kroening/frontend-issue5

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import some_pkg::*; was a syntax error unless the file declaring some_pkg
happened to be given earlier on the command line, and the diagnostic named a
token class rather than the package.

IEEE 1800-2017 26.3 requires that the compilation of a package precedes the
compilation of the scopes in which the package is imported, but the standard
does not prescribe an order for the input files, and command files produced by
other tools do not generally list a package ahead of its importers.

Example, which previously failed in one of the two orders:

// A.sv
package some_pkg;
  typedef logic [3:0] some_type;
endpackage
// B.sv
import some_pkg::*;
module top;
  some_type x;
  initial assert($bits(x) == 4);
endmodule

Ordering

Identifiers are classified by the scanner, which consults the scope table, and
hence the members of an imported package must be in scope while the importing
file is scanned. Accepting the import and resolving it later is therefore not
sufficient: some_type above would still not be classified as a type name.

Instead, a scanner-only pre-pass over the preprocessed input records the
packages that each file declares and the packages that it references. A
topological sort then gives the order in which the files are parsed and
elaborated. Files without such a dependency retain their relative order, and
the parse trees are returned in the order in which the files were given, so
the choice of top-level modules is unaffected. Transitive chains, i.e., a
package that itself imports another package, are handled. A dependency cycle,
which is illegal, is broken arbitrarily, and the parser then reports the
offending reference.

Diagnostic

The operand of an import can only ever be a package name. The grammar now also
accepts an identifier that the scanner did not classify as a package name, and
reports

file B.sv line 1: unknown package `no_such_package'

or, when the name denotes something other than a package,

file B.sv line 3: `m' is not a package

There are no new grammar conflicts.

Tests

New tests in regression/verilog/packages: two_files2, two_files3 (a
wildcard import and an explicit import, with the package given after the
importing file), three_files1 (a chain of two packages, files given in
reverse dependency order), and import10, import11 for the diagnostic on a
package that is not declared.

@kroening
kroening marked this pull request as draft August 11, 2026 18:28
IEEE 1800-2017 26.3 requires that the compilation of a package precedes
the compilation of the scopes in which the package is imported, but the
standard does not prescribe an order for the input files.  We hence
determine the order in which the input files are parsed and elaborated
from the packages that they declare and reference, using a scanner-only
pre-pass over the preprocessed input.  The parse trees are still
returned in the order in which the files were given, so that the choice
of top-level modules is unaffected.

Furthermore, the operand of an import can only ever be a package name,
and hence the grammar now also accepts an identifier that is not
classified as a package name.  That yields a diagnostic that names the
offending package instead of a syntax error about a token class.
@kroening
kroening force-pushed the kroening/frontend-issue5 branch from dbb8dc6 to 78ef0bd Compare August 11, 2026 18:33
Library files are parsed after the given files, and hence are appended to
the list of parse trees once the given files have been parsed. Extend the
elaboration order accordingly, as it would otherwise not cover them, and
add an invariant that the elaboration order covers all parse trees.
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