Verilog: simulation time system functions - #2092
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Per 1800-2017 20.3, add support for $time, $stime and $realtime, which previously gave "unknown system function". The types of the results follow 1800-2017 20.3: $time yields a 64-bit integer, $stime yields the low-order 32 bits thereof, and $realtime yields a real. EBMC has no notion of continuous simulation time: delay controls are ignored, and so are `timescale and timeunit. The simulation time is therefore modelled by a global state variable that counts the timeframes, i.e., the time advances by exactly one time unit per timeframe. Consequently, the absolute times reported will not match those of an event-driven simulator when delays or a timescale are given.
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August 12, 2026 11:50
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This adds support for the simulation time system functions of IEEE
1800-2017 clause 20.3, i.e.,
$time,$stimeand$realtime.Root cause
These three functions were simply absent from the system function
dispatch in
verilog_typecheck_exprt::convert_system_function, and hencethe final
elsebranch rejected them withThere was no synthesis support for them either.
Semantics
The result types follow 1800-2017 20.3:
$time(20.3.1) is a 64-bit integer,$stime(20.3.3) is the low-order 32 bits thereof, i.e., a 32-bitunsigned integer,
$realtime(20.3.2) is a real. Note that 1800-2017 6.12.1 makesrealtimea synonym ofreal.EBMC has no notion of continuous simulation time: there is no event
queue, delay controls are ignored, and
`timescale/timeunitarenot taken into account. The model of time is the sequence of timeframes
of the transition system. We therefore let the time advance by exactly
one time unit per timeframe, and model the simulation time using a
global state variable
$root.$timeof typeunsignedbv[64]that iscreated on first use, with
$timereads that variable,$stimeis a truncating cast to 32 bits(which is exactly the "low-order 32 bits" of 20.3.3), and
$realtimeis a conversion to
floatbvusing the same rounding mode as thelowering of integer-to-real casts.
Using an ordinary state variable rather than a new IR node means that no
backend changes are required: this works for word-level BMC, the
bit-level/AIG engine, BDDs, k-induction, IC3 and new-IC3, as well as for
the
--smv-word-level,--verilog-rtland--show-transoutputbackends. This was checked for each of these engines.
Limitations
`timescale,timeunitand#delayare ignored, and hence absolute times will not agree with an
event-driven simulator when these are used.
the invoking module.
$timeis given the two-valued typeunsignedbv[64]rather than thefour-valued
timetype, as the value is always known.$bits($realtime)still fails, as$bitsdoes not supportreal;this is pre-existing and independent of this change.
real-typed variable in a property still trips aninvariant in
boolbv_equality; this too is pre-existing (it reproduceswithout
$realtime) and is not addressed here.Tests
This fixes the
KNOWNBUGtest added in #2087, which is turned into aCOREtest, and adds teststime1,stime1andrealtime2coveringthe value of the time in successive timeframes, the widths of the
results, and a refuted property.