Verilog: assignments between unpacked arrays of equivalent types - #2100
Draft
kroening wants to merge 1 commit into
Draft
Verilog: assignments between unpacked arrays of equivalent types#2100kroening wants to merge 1 commit into
kroening wants to merge 1 commit into
Conversation
kroening
marked this pull request as draft
August 12, 2026 21:07
kroening
marked this pull request as ready for review
August 12, 2026 22:45
kroening
marked this pull request as draft
August 12, 2026 22:45
kroening
changed the base branch from
kroening/knownbug-array-of-structs-port
to
main
August 13, 2026 09:11
Per 1800-2017 section 7.6, an unpacked array can be assigned an unpacked array of an equivalent type, and section 6.22.1 gives the rules for type equivalence: fixed-size unpacked arrays are equivalent when they have the same size and equivalent element types, and packed arrays, packed structs, packed unions and the built-in integral types are equivalent when they have the same number of bits, the same 2-state/4-state property, and the same signing. An unpacked array of a packed struct that is eight bits wide can therefore be assigned to, or connected to a port of, an unpacked array of [7:0]. The type checker now implements this equivalence rule, and inserts a typecast where the two types are equivalent but not identical. The lowering of a typecast to a struct, union or array passed the operand to from_bitvector without converting it to a bit vector first, which tripped a precondition in extract when the operand was itself of a composite type; this now goes through to_bitvector, which leaves non-composite operands unchanged. Note that the elaborated types do not record whether a vector was declared as 2-state or 4-state, and hence the 2-state/4-state condition only rules out the types that carry x and z.
kroening
force-pushed
the
kroening/fix-array-of-structs-port
branch
from
August 13, 2026 15:29
df4878e to
094aebd
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Fixes the KNOWNBUG from #2099. Based on #2099, please merge that one first.
Per 1800-2017 section 7.6, an unpacked array can be assigned an unpacked array of
an equivalent type, and section 6.22.1 gives the equivalence rules:
equivalent element types;
types are equivalent when they have the same number of bits, are all 2-state or
all 4-state, and are all signed or all unsigned.
An unpacked array of an eight-bit packed struct is therefore assignable to, and
connectable to a port of, an unpacked array of
[7:0].Changes
src/verilog/verilog_typecheck_expr.cpp— newequivalent_typeimplementing 6.22.1, with
is_integral_type(6.11.1) andis_signed_type(7.2.1, 7.4.1) helpers.
assignment_conversionnow inserts a typecast wherethe two unpacked array types are equivalent but not identical, instead of
rejecting the assignment.
src/verilog/verilog_lowering.cpp— the lowering of a typecast to astruct, union or array passed the operand to
from_bitvectorwithoutconverting it to a bit vector first, which tripped the
src.type().id() != ID_arrayprecondition inextractonce the operand was itself of a compositetype. It now goes through
to_bitvector, which returns non-composite operandsunchanged, so the existing paths are unaffected.
Note that the elaborated types do not record whether a vector was declared as
2-state or 4-state (
logic [7:0]andbit [7:0]both elaborate to the sametype), so the 2-state/4-state condition only rules out the types that carry x
and z. This is noted in a comment.
Tests
structs/array_of_structs2— flipped KNOWNBUG to CORE (the reported portconnection).
structs/array_of_structs3— new CORE test asserting the conversion in bothdirections, checking the order of the array elements and the order of the
struct members, using a two-field struct against
[15:0]so a swap would becaught.
structs/array_of_structs4— new CORE test that non-equivalent element widthsare still rejected.
Also checked by hand, and still rejected: array size mismatch, signedness
mismatch, and an unpacked struct as the element type. Nested
array of array of structworks via the recursive case.Full
regression/{verilog,ebmc,smv,vlindex}in-Cand-Kmodes plus the unittests pass.