Verilog: implicit nets for concatenation members on continuous-assign LHS

regression/verilog/continuous_assign_implicit_net1/main.v

@@ -0,0 +1,15 @@
+// An undeclared identifier used as a member of a concatenation on the LHS
+// of a continuous assignment is implicitly declared as a scalar net of the
+// default net type (IEEE 1800-2017 6.10). Here `cout` is never declared;
+// it is the discarded carry-out of the subtraction.
+// Regression for LogikBench arithmetic/sub.
+module main #(parameter DW = 16)
+  (
+   input [DW-1:0]  a,
+   input [DW-1:0]  b,
+   output [DW-1:0] out
+   );
+
+  assign {cout, out[DW-1:0]} = a[DW-1:0] - b[DW-1:0];
+
+endmodule

regression/verilog/continuous_assign_implicit_net1/test.desc

@@ -0,0 +1,8 @@
+CORE
+main.v
+--module main --bound 0
+^Type-checking Verilog::main$
+^EXIT=10$
+^SIGNAL=0$
+--
+^.*unknown identifier cout.*$

src/verilog/verilog_typecheck.cpp

@@ -820,6 +820,22 @@ void verilog_typecheckt::convert_continuous_assign(
       lhs = convert_verilog_identifier(
         to_verilog_identifier_expr(lhs), unsignedbv_typet{1});
     }
+    else if(lhs.id() == ID_concatenation)
+    {
+      // The implicit net rule also applies to undeclared identifiers that
+      // appear as members of a concatenation on the LHS, e.g.
+      //   assign {carry, sum} = a + b;   // carry is undeclared
+      // Declare each such member as a scalar net of the default net type,
+      // then convert the concatenation as usual.
+      for(auto &op : lhs.operands())
+      {
+        if(op.id() == ID_verilog_identifier)
+          op = convert_verilog_identifier(
+            to_verilog_identifier_expr(op), unsignedbv_typet{1});
+      }
+
+      convert_expr(lhs);
+    }
     else
       convert_expr(lhs);