I have a design with matrix of DSPs that is supposed to re-use the DSP cell. I name each with instantiation of the DSP cell using setattr to make them easy to track down during VCD traces like so:
arr = []
for r in range(Params["rows"]):
temp = []
for c in range(Params["cols"]):
#add cell as named submodule
cell = Cell(WIDTH=Params["WIDTH"])
setattr(m.submodules,f"cell_r{r}_c{c}",cell)
#externally expose sums
m.d.comb += self.sums[r][c].eq(cell.SUM)
temp.append(cell)
arr.append(temp)When I have nmigen convert to verilog however, an identical verilog module is created for each cell as shown below:
cell_r1_c0 cell_r1_c0 (
.F_down(cell_r1_c0_F_down),
.F_right(cell_r1_c0_F_right),
.L_in(cell_r1_c0_L_in),
.SUM(cell_r1_c0_SUM),
.Top_in(cell_r1_c0_Top_in),
.clk(clk),
.rst(rst)
);
cell_r1_c1 cell_r1_c1 (
.F_down(cell_r1_c1_F_down),
.F_right(cell_r1_c1_F_right),
.L_in(cell_r1_c1_L_in),
.SUM(cell_r1_c1_SUM),
.Top_in(cell_r1_c1_Top_in),
.clk(clk),
.rst(rst)
);
cell_r1_c2 cell_r1_c2 (
.F_down(cell_r1_c2_F_down),
.F_right(cell_r1_c2_F_right),
.L_in(cell_r1_c2_L_in),
.SUM(cell_r1_c2_SUM),
.Top_in(cell_r1_c2_Top_in),
.clk(clk),
.rst(rst)
);Is it possible to have the emitted verilog re-use one DSP cell?
I guess one question one could always ask is how could nMigen know one instantiation of a DSP cell is identical to the next.
I have a design with matrix of DSPs that is supposed to re-use the DSP cell. I name each with instantiation of the DSP cell using
setattrto make them easy to track down during VCD traces like so:When I have nmigen convert to verilog however, an identical verilog module is created for each cell as shown below:
cell_r1_c0 cell_r1_c0 ( .F_down(cell_r1_c0_F_down), .F_right(cell_r1_c0_F_right), .L_in(cell_r1_c0_L_in), .SUM(cell_r1_c0_SUM), .Top_in(cell_r1_c0_Top_in), .clk(clk), .rst(rst) ); cell_r1_c1 cell_r1_c1 ( .F_down(cell_r1_c1_F_down), .F_right(cell_r1_c1_F_right), .L_in(cell_r1_c1_L_in), .SUM(cell_r1_c1_SUM), .Top_in(cell_r1_c1_Top_in), .clk(clk), .rst(rst) ); cell_r1_c2 cell_r1_c2 ( .F_down(cell_r1_c2_F_down), .F_right(cell_r1_c2_F_right), .L_in(cell_r1_c2_L_in), .SUM(cell_r1_c2_SUM), .Top_in(cell_r1_c2_Top_in), .clk(clk), .rst(rst) );Is it possible to have the emitted verilog re-use one DSP cell?
I guess one question one could always ask is how could nMigen know one instantiation of a DSP cell is identical to the next.