Fix register field widths

data/registers/cpuss_v1.yaml

@@ -128,23 +128,23 @@ fieldset/MIS:
   - name: INT
     description: Masked interrupt status for INT.
     bit_offset: 0
-    bit_size: 1
+    bit_size: 8
     enum: MIS
 fieldset/ISET:
   description: Interrupt set.
   fields:
   - name: INT
     description: Sets INT in RIS register.
     bit_offset: 0
-    bit_size: 1
+    bit_size: 8
     enum: ISET
 fieldset/ICLR:
   description: Interrupt clear.
   fields:
   - name: INT
     description: Clears INT in RIS register.
     bit_offset: 0
-    bit_size: 1
+    bit_size: 8
     enum: ICLR
 
 enum/IIDX:
@@ -196,7 +196,7 @@ enum/RIS:
     description: INT occurred.
     value: 1
 enum/MIS:
-  bit_size: 1
+  bit_size: 8
   variants:
   - name: CLR
     description: INT does not request an interrupt service routine.
@@ -205,7 +205,7 @@ enum/MIS:
     description: INT requests an interrupt service routine.
     value: 1
 enum/ISET:
-  bit_size: 1
+  bit_size: 8
   variants:
   - name: NO_EFFECT
     description: Writing a 0 has no effect.
@@ -214,7 +214,7 @@ enum/ISET:
     description: RIS bit corresponding to INT is set.
     value: 1
 enum/ICLR:
-  bit_size: 1
+  bit_size: 8
   variants:
   - name: NO_EFFECT
     description: Writing a 0 has no effect.

data/registers/gpio_v1.yaml

@@ -422,14 +422,17 @@ fieldset/FPORT:
     bit_offset: 0
     bit_size: 4
 fieldset/GEN_EVENT:
-  description: Interrupt clear.
+  # Indexed by absolute DIO number, so that it agrees with CPU_INT and the DOUT/DIN masks.
+  # GEN_EVENT0 implements DIO0 to DIO15 and GEN_EVENT1 implements DIO16 to DIO31, each at the bit
+  # matching its own DIO number; the other half of the word is reserved in both.
+  description: Generic event mask, one bit per DIO.
   fields:
   - name: DIO
-    description: DIO0 event.
+    description: DIO event.
     bit_offset: 0
     bit_size: 1
     array:
-      len: 16
+      len: 32
       stride: 1
 fieldset/GEN_EVENT_IIDX:
   description: Interrupt index.