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shreyas-damn/README.md

Watashi wa, Shreyas des

🎓 Electronics & Telecommunications Undergraduate
⚡ Interested in Analog Circuit Design, VLSI & Embedded Systems
💻 Exploring Digital Design, Verilog, LTspice & System Architecture

Watashi no interests

  • RTL design & verification (Verilog)
  • EDA Tools
  • PCB Design

Pinned Loading

  1. UART-RTL-TO-GDSII UART-RTL-TO-GDSII Public

    Universal Asynchronous Receiver - Transmitter Communication Protocol using Verilog / System-Verilog

    Verilog 1

  2. RISC-V-32I-Single-Staged-Processor RISC-V-32I-Single-Staged-Processor Public

    A HDL implementation of a single-cycle RISC-V (RV32I) processor that performs instruction fetch, decode, execute, memory access, and write-back in a single clock cycle.

    Verilog 1

  3. 2-way-traffic-light-FSM-using-Xilinx-Vivado 2-way-traffic-light-FSM-using-Xilinx-Vivado Public

    C

  4. 4-bit-Carry-Look-Ahead-Adder 4-bit-Carry-Look-Ahead-Adder Public

    Design and Synthesis of 4 bit Carry Look Ahead Adder using Cadence Xcelium and Genus

    Stata

  5. Asynchronous-FIFO Asynchronous-FIFO Public

    Verilog