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Add RISC-V MCUs as a supported MCU class #99
Description
Summary
Track RISC-V MCUs as a first-class Silico MCU class (host plate, doctor, inspect, deploy, first-ship metal notes).
Today Silico ships RP2040-class and ESP32-class only. RISC-V is the open-ISA family with a growing ecosystem for next-generation embedded systems, IoT, and edge AI — not yet a Silico spine target as a named class.
Note: Some ESP32 variants (e.g. C3/C6) are RISC-V under the hood; those stay under ESP32-class + esptool/ESP-IDF today. This issue is for non-Espressif (or generic) RISC-V MCU support as its own spine class — e.g. GD32V, CH32V, RP2350-RISC-V paths if forced separately, SiFive-class, etc. — not a re-label of existing ESP tooling.
Why it matters
| Strength | Typical GCU shape |
|---|---|
| Open ISA, growing ecosystem, modern architectures | Next-generation embedded, IoT, AI at the edge |
| Vendor diversity | Products choosing open-ISA silicon for cost, licensing, or long-term control |
What "supported" should mean (proposal)
Same operator experience as other classes; different plumbing:
| Verb / concern | RISC-V MCU shape (sketch) |
|---|---|
silico.toml |
MCU class + vendor/board; toolchain pin (GCC RISC-V, OpenOCD, vendor flash, Zephyr, or MicroPython if available) |
| Doctor | Toolchain + probe/serial discovery in plain language |
| Inspect | Serial or SWD/JTAG identity contract |
| Deploy | Image flash after operator yes; progress streaming |
| Gate | Host-side domain tests; HAL seam honest |
| Plate | Thin hello-metal for the first forced board, not a universal RISC-V mega-plate |
| BEDSIDE / knowledge | First-flash per vendor; do not invent pin folklore |
Non-goals (first slice)
- Soft-forking Bedside into a RISC-V essay.
- Claiming “all RISC-V” support in one PR — first landing is one vendor board.
- Re-homing ESP32-C3/C6 work out of ESP32-class without a good reason.
- Claiming platform status without a GCU that ships on the chosen board.
Sequencing
Extract, then open when a real GCU forces a RISC-V MCU outside the ESP spine. Prefer naming the board + flash tool in the first proof issue comment, then implement.
Done when
-
silico.toml/ doctor document the first RISC-V MCU class board and tools. - Deploy plans/runs flash with operator gates.
- Inspect identity works for the chosen runtime.
- Plate or documented first-ship path for that board.
- AGENTS/BEDSIDE/knowledge leave-behind for first-flash + product face.
- At least one real board proof.
- Clear boundary vs ESP32-class RISC-V variants documented.
References
- Related: ESP32-class path (already shipped); silicov1 multi-target later
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