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nuttx: rework atomic operations - #19802

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nuttx: rework atomic operations#19802
zhangyu-duck wants to merge 7 commits into
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zhangyu-duck:atomic-upstream

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@zhangyu-duck zhangyu-duck commented Aug 12, 2026

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Summary

This PR reworks the atomic operation implementation in <nuttx/atomic.h> to provide a unified, portable, and standard-conflict-free atomic interface.

Key changes:

  1. Use toolchain builtin atomic functions instead of /<stdatomic.h>. The original implementation relied on __has_include() and C11 version checks, which is not portable (e.g., Tasking compiler doesn't support __has_include). It
    also conflicts with third-party C++ libraries that include — the standard library expects template types while NuttX atomic_t is int32_t, causing compile errors. The new implementation calls compiler builtins (_atomic* / _c11_atomic*
    / _Interlocked*) directly, similar to Zephyr.
  2. Rename atomic_fetch_xxx to atomic_xxx (e.g., atomic_fetch_add → atomic_add). The atomic_fetch_xxx naming is reserved by the C/C++ standard. Since source files may directly or indirectly include <nuttx/atomic.h>, keeping the standard name
    causes function name conflicts and compile errors. Other non-standard API names (e.g., atomic_read, atomic_set, atomic_xchg) remain unchanged.
  3. Add four selectable atomic backends via Kconfig:
    - LIBC_ATOMIC_TOOLCHAIN — compiler builtins (default, lock-free)
    - LIBC_ATOMIC_ARCH — arch-native atomic instructions (lock-free)
    - LIBC_ATOMIC_HWSPINLOCK — hardware spinlock wrapping critical section (cross-core, for chips without atomic instructions but with hwspinlock peripheral)
    - LIBC_ATOMIC_IRQ — IRQ disable wrapping critical section (single-core only, fallback for ARMv6-M / ARM7TDMI / ARM926EJS etc.)
  4. Add hwspinlock-based atomic for cxd56, rp2040, and lc823450 (multi-core capable chips).
  5. Use _Atomic qualifier for atomic_t typedef when the compiler supports it, with a __Atomic(t) wrapper for clang compatibility.

@zhangyu-duck
zhangyu-duck marked this pull request as draft August 12, 2026 07:52
@jerpelea jerpelea changed the title Atomic upstream nuttx: rework atomic operations Aug 12, 2026
jerpelea
jerpelea requested changes Aug 12, 2026
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please follow contribution guidelines and provide proper PR description, impact and testing

@github-actions github-actions Bot added Area: Bluetooth Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture labels Aug 12, 2026
@github-actions github-actions Bot added Arch: xtensa Issues related to the Xtensa architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Aug 12, 2026
@github-actions

github-actions Bot commented Aug 12, 2026 •
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MemBrowse Memory Report

arduino-mega2560

@zhangyuduck
nuttx/libc: The atomic implementation of machine/arch_atomic.c should…
1cf66ca 
… be achieved by switching interrupts, this version does not support SMP

VELAPLATFO-66334

Change-Id: I0817567aabfa370a8eb7798b0a5ab8c8f2e550b2
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/libc: refine the atomic related Kconfig
8e8e118 
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@github-actions github-actions Bot added Area: OS Components OS Components issues and removed Area: Bluetooth Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: simulator Issues related to the SIMulator labels Aug 14, 2026
@zhangyuduck
nuttx/atomic: select LIBC_ATOMIC_IRQ for archs without atomic support
a2cef40 
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.

Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/hwspinlock: hwspinlock should based on irq instead of spinlock_irq
c5220e7 
VELAPLATFO-77769

Change-Id: I88642ef6b8882eabc98169aeabb8dd8f22e0ae7c
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: add hwspinlock driver for cxd56, rp2040 and lc823450
75eb5e7 
Add hardware spinlock driver implementations for cxd56, rp2040, and
lc823450 chips. These drivers provide the hwspinlock_ops_s interface
used by the atomic hwspinlock backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
libc/machine: realize atomic based on hwspinlock
81ce0ac 
Implement atomic_lock/atomic_unlock using hwspinlock when
CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/
up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename
arch_atomic_irq.c to arch_atomic.c.

Select LIBC_ATOMIC_HWSPINLOCK for SMP on RP2040 which has hardware
spinlock support for multi-core atomic operations.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: realize atomic for cxd56, rp2040 and lc823450
7995fa4 
Add per-chip atomic hwspinlock device definitions for cxd56, rp2040,
and lc823450. These provide the hardware spinlock device used by the
atomic hwspinlock backend for multi-core atomic operations.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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Arch: arm Issues related to ARM (32-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Area: OS Components OS Components issues Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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