nuttx: rework atomic operations

arch/arm/Kconfig

@@ -382,6 +382,8 @@ config ARCH_CHIP_RP2040
 	select ARCH_BOARD_COMMON
 	select ARCH_HAVE_CUSTOM_TESTSET
 	select ARCH_USBDEV_STALLQUEUE if USBDEV
+	select LIBC_ATOMIC_IRQ if !SMP
+	select LIBC_ATOMIC_HWSPINLOCK if SMP
 	---help---
 		Raspberry Pi RP2040 architectures (ARM dual Cortex-M0+).
 
@@ -928,7 +930,7 @@ config ARCH_CHIP_CXD32XX
 	bool "Sony CXD32xx"
 	select ARCH_CORTEXM4
 	select ARCH_HAVE_FPU
-	select LIBC_ARCH_ATOMIC
+	select LIBC_ATOMIC_IRQ
 	---help---
 		Sony CXD32XX (ARM Cortex-M4) architectures
 
@@ -960,6 +962,7 @@ config ARCH_ARM7TDMI
 	default n
 	select ARCH_DCACHE
 	select ARCH_ICACHE
+	select LIBC_ATOMIC_IRQ
 	---help---
 		The Arm7TDMI-S is an excellent workhorse processor capable of a wide
 		array of applications. Traditionally used in mobile handsets, the
@@ -989,6 +992,7 @@ config ARCH_ARM926EJS
 	select ARCH_ICACHE
 	select ARCH_HAVE_MMU
 	select ARCH_USE_MMU
+	select LIBC_ATOMIC_IRQ
 	---help---
 		Arm926EJ-S is the entry point processor capable of supporting full
 		Operating Systems including Linux, WindowsCE, and Symbian.
@@ -1044,6 +1048,7 @@ config ARCH_ARMV6M
 	bool
 	default n
 	select ARCH_HAVE_CPUINFO
+	select LIBC_ATOMIC_IRQ if !LIBC_ATOMIC_HWSPINLOCK
 
 config ARCH_CORTEXM0
 	bool

arch/arm/src/cxd56xx/CMakeLists.txt

@@ -39,144 +39,183 @@ set(SRCS
     cxd56_icc.c
     cxd56_powermgr.c
     cxd56_farapi.c
-    cxd56_sysctl.c)
+    cxd56_sysctl.c
+    cxd56_hwspinlock.c)
 
 if(CONFIG_SMP)
   list(APPEND SRCS cxd56_cpuidlestack.c)
+list(APPEND SRCS cxd56_atomic.c)
   list(APPEND SRCS cxd56_smpcall.c)
+list(APPEND SRCS cxd56_atomic.c)
   list(APPEND SRCS cxd56_cpustart.c)
+list(APPEND SRCS cxd56_atomic.c)
   if(CONFIG_CXD56_TESTSET)
     list(APPEND SRCS cxd56_testset.c)
+list(APPEND SRCS cxd56_atomic.c)
   endif()
 endif()
 
 if(CONFIG_ARCH_HAVE_MULTICPU)
   list(APPEND SRCS cxd56_cpuindex.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_ARCH_USE_TEXT_HEAP)
   list(APPEND SRCS cxd56_textheap.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_UART0)
   list(APPEND SRCS cxd56_uart0.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_PM_PROCFS)
   list(APPEND SRCS cxd56_powermgr_procfs.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_RTC)
   list(APPEND SRCS cxd56_rtc.c)
+list(APPEND SRCS cxd56_atomic.c)
   if(CONFIG_RTC_DRIVER)
     list(APPEND SRCS cxd56_rtc_lowerhalf.c)
+list(APPEND SRCS cxd56_atomic.c)
   endif()
 endif()
 
 if(CONFIG_CXD56_GPIO_IRQ)
   list(APPEND SRCS cxd56_gpioint.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_USBDEV)
   list(APPEND SRCS cxd56_usbdev.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_SDIO)
   list(APPEND SRCS cxd56_sdhci.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_SFC)
   list(APPEND SRCS cxd56_sfc.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_SPH)
   list(APPEND SRCS cxd56_sph.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_EMMC)
   list(APPEND SRCS cxd56_emmc.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_SPI)
   list(APPEND SRCS cxd56_spi.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_I2C)
   list(APPEND SRCS cxd56_i2c.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_I2C_BITBANG)
   list(APPEND SRCS cxd56_i2c_bitbang.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_DMAC)
   list(APPEND SRCS cxd56_dmac.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_PWM)
   list(APPEND SRCS cxd56_pwm.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_GAUGE)
   list(APPEND SRCS cxd56_gauge.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_CHARGER)
   list(APPEND SRCS cxd56_charger.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_AUDIO_CXD56)
   list(APPEND SRCS cxd56_nxaudio.c)
+list(APPEND SRCS cxd56_atomic.c)
   if(CONFIG_AUDIO_CXD56_SRC)
     list(APPEND SRCS cxd56_nxaudio_src.c)
+list(APPEND SRCS cxd56_atomic.c)
   endif()
 endif()
 
 if(CONFIG_CXD56_GE2D)
   list(APPEND SRCS cxd56_ge2d.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_CISIF)
   list(APPEND SRCS cxd56_cisif.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_SCU)
   list(APPEND SRCS cxd56_scu.c cxd56_scufifo.c)
+list(APPEND SRCS cxd56_atomic.c)
   if(CONFIG_CXD56_ADC)
     list(APPEND SRCS cxd56_adc.c)
+list(APPEND SRCS cxd56_atomic.c)
   endif()
   if(CONFIG_CXD56_UDMAC)
     list(APPEND SRCS cxd56_udmac.c)
+list(APPEND SRCS cxd56_atomic.c)
   endif()
 endif()
 
 if(CONFIG_CXD56_TIMER)
   list(APPEND SRCS cxd56_timer.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_WDT)
   list(APPEND SRCS cxd56_wdt.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_GNSS)
   list(APPEND SRCS cxd56_gnss.c)
+list(APPEND SRCS cxd56_atomic.c)
   list(APPEND SRCS cxd56_cpu1signal.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_GEOFENCE)
   list(APPEND SRCS cxd56_geofence.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_BACKUPLOG)
   list(APPEND SRCS cxd56_backuplog.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_HOSTIF)
   list(APPEND SRCS cxd56_hostif.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 if(CONFIG_CXD56_GNSS_HEAP)
   list(APPEND SRCS cxd56_gnssheap.c)
+list(APPEND SRCS cxd56_atomic.c)
 endif()
 
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/cxd56xx/Make.defs

@@ -39,6 +39,8 @@ CHIP_CSRCS += cxd56_icc.c
 CHIP_CSRCS += cxd56_powermgr.c
 CHIP_CSRCS += cxd56_farapi.c
 CHIP_CSRCS += cxd56_sysctl.c
+CHIP_CSRCS += cxd56_atomic.c
+CHIP_CSRCS += cxd56_hwspinlock.c
 
 ifeq ($(CONFIG_SMP),y)
 CHIP_CSRCS += cxd56_cpuidlestack.c

arch/arm/src/cxd56xx/cxd56_atomic.c

@@ -0,0 +1,50 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_atomic.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SPH_SMP  14
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern const struct hwspinlock_ops_s g_cxd56_hwspinlock_ops;
+
+struct hwspinlock_dev_s g_atomic_hwspinlock =
+{
+  .id       = SPH_SMP,
+  .priority = 0,
+  .ops      = &g_cxd56_hwspinlock_ops
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/

arch/arm/src/cxd56xx/cxd56_hwspinlock.c

@@ -0,0 +1,63 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_hwspinlock.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+#include "arm_internal.h"
+#include "hardware/cxd56_sph.h"
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static bool cxd56_hwspinlock_trylock(struct hwspinlock_dev_s *dev);
+static void cxd56_hwspinlock_unlock(struct hwspinlock_dev_s *dev);
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+const struct hwspinlock_ops_s g_cxd56_hwspinlock_ops =
+{
+  .trylock = cxd56_hwspinlock_trylock,
+  .unlock  = cxd56_hwspinlock_unlock
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static bool cxd56_hwspinlock_trylock(struct hwspinlock_dev_s *dev)
+{
+  uint32_t sphlocked = ((up_cpu_index() + 2) << 16) | 0x1;
+
+  putreg32(REQ_LOCK, CXD56_SPH_REQ(dev->id));
+
+  return getreg32(CXD56_SPH_STS(dev->id)) == sphlocked;
+}
+
+static void cxd56_hwspinlock_unlock(struct hwspinlock_dev_s *dev)
+{
+  putreg32(REQ_UNLOCK, CXD56_SPH_REQ(dev->id));
+}

arch/arm/src/cxd56xx/cxd56_sph.c

@@ -272,7 +272,7 @@ int cxd56_sphinitialize(const char *devname)
 
   /* No. 0-2 and (14)-15 semaphores are reserved by other system. */
 
-#ifdef CONFIG_CXD56_TESTSET
+#ifdef CONFIG_CXD56_ATOMIC_WITH_HWSEM
   for (i = 3; i < 14; i++)
 #else
   for (i = 3; i < 15; i++)

arch/arm/src/lc823450/Make.defs

@@ -25,6 +25,7 @@ include armv7-m/Make.defs
 CHIP_CSRCS  = lc823450_allocateheap2.c lc823450_start.c lc823450_irq.c lc823450_timer.c
 CHIP_CSRCS += lc823450_lowputc.c lc823450_serial.c lc823450_clockconfig.c
 CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c
+CHIP_CSRCS += lc823450_hwspinlock.c
 
 # Configuration-dependent LC823450 files
 
@@ -123,3 +124,4 @@ endif
 ifeq ($(CONFIG_ARM_MPU),y)
 CHIP_CSRCS += lc823450_mpuinit2.c
 endif
+CHIP_CSRCS += lc823450_atomic.c