test-bench

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Test bench to measure and investigate performance of Apache Maven project

A DAQ framework to enable complex measurement scenarios.

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

The Puppet Master for Embedded Target Boards: Dual-CDC USB test harness with MicroPython REPL & UART streaming bridge

Hardware-in-the-Loop (HIL) automation gateway and FastMCP server for embedded target boards

Wireless ESP32-S3 test bench: control pins, PWM, servos, a live scope and I2C tools from your browser

Implementation of a Parameterized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Hardware and software for a BLDC thrust and torque measurement system using STM32.

A slim PyQt5 Python desktop tool for real-time visualization and CSV/XLSX logging of GSV-6 / GSV-8 CAN measurement amplifiers using a dynamic device-channel tree view.

Banc de Mesure Botafumeiro - Excitation Paramétrique d'un Pendule

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Laboratory test bench for testing and evaluating high-voltage semiconductor components and materials. Features a custom 12V-to-100V Boost converter, thermal simulations, and 3D-printed enclosure.

Automate hardware and software tests in Rust. Run parameter sweeps, capture live measurements, and generate self-contained HTML reports.

This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

Designed, simulated, 3D-printed, and experimentally tested a manually variable-pitch propeller system — from blade theory and CAD through CFD validation to a self-built RPM and thrust measurement rig.

Production-grade Automated Test Equipment (ATE) Execution Framework with Hardware Abstraction Layer (HAL), multi-threading, and compliance reporting.

Web-based CANopen test bench and machine control: scan nodes, read/write SDOs from EDS files, run YAML test cases, flash firmware and trace the bus live. Python/python-can with IXXAT, PCAN and Vector adapters; demo mode needs no hardware.

Describe an instrument in YAML and this serves it over its real protocol. Your test software talks SCPI to a Keithley that doesn't exist. Built so you can try a test bench without owning one.